工学学士(半导体物理与器件)，清华大学，中国，1983。

工学硕士(计算机应用)，清华大学，中国，1986。

工学博士(计算机应用)，中国科学技术大学，中国，2007。

清华大学计算机系软件与理论研究所工作(2008-)。

清华大学计算机系分学术委员会任职(2008-)。

Integration, VLSI of Journal：编委(2009-2011)。

《半导体学报》：编委(2009-2011)。

国家“核高基”科技重大专项：先进EDA工具平台开发(2008-2010)。

国家自然科学基金海外青年合作：考虑工艺参数变化的IC设计优化理论与关键技术(2009-2010)。

国家自然科学基金：极大规模集成电路片上供电网络仿真及优化(2008-2010)。

国家自然科学基金：纳米工艺下集成电路自动布线算法研究(2010-2012)。

[1] J. Shi, Y. C. Cai, W. T. Hou, L. W. Ma, S. X.-D. Tan, P-H. Ho, X. Y. Wang, GPU friendly Fast Poisson Solver for Structured Power Grid Network Analysis, in Proc. Design Automation Conference (DAC 2009), San Francisco, USA, July 2009, PP.178-183. (Best Paper Nomination)

[2] J. Shi, Y. C. Cai, S. X.-D. Tan, X. L. Hong, High Accurate Pattern Based Precondition Method for Extremely Large Power/Ground Grid Analysis, in Prof. International Symposium on Physical Design (ISPD 2006), San Jose, USA, April 2006, PP.108-113.

[3] J. Shi, Y. C. Cai, S. X.-D. Tan, J. Fan, X. L. Hong, Pattern Based Iterative Method for Extreme Large Power/Ground Analysis, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems(TCAD), Vol.26, No.4, PP. 680-692, 2007.

[4] X. Y. Wang, Y. C. Cai, S. X.-D. Tan, Decoupling Capacitance Budgeting Aware Placement For Transient Power Supply Noise Elimination, in Proc. Integrated Circuit Computer Aided Design (ICCAD 2009), San Jose, USA, Nov. 2009, PP. 745-751.

[5] X. Y. Wang, Y. C. Cai, S. X.-D. Tan, X. L. Hong, J. Relles, An Efficient Decoupling Capacitance Optimization Using Piecewise Polynomial Models. in Proc. ACM/IEEE Design, Automation & Test in Europe Conference (DATE 2009), Nice, France, April 2009, PP.1190–1195.

[6] Y. C. Cai, L. Kang, J. Shi, X. L. Hong, S. X.-D. Tan, Random Walk Based Optimization Approach for Power/Ground Network, IEEE Trans. on Circuits and Systems II(TCAS-II), Vol. 55, No. 1, PP. 36-40, 2008.

[7] Cai Yici, Fu Jingjing, Hong Xianlong, S. X._D. Tan and Z. Lou Power/Ground Network Optimization Considering Decap Leakage Currents, IEEE Trans. On Circuit and System (TCAS-II), Vol.53, No. 10, pp1012-1016, 2006.

[8] Guo Liangpeng, Cai Yici, Zhou Qiang, Hong Xianlong, Performance Driven Power Gating Based on Distributed Sleep Transistor Network, Proceedings of the 2008 ACM Great Lakes Symposium on VLSI (SGLVLSI 2008), Orlando, Florida, USA, May 2008, pp255-260. (Best Paper Award)

[9] Y. C. Cai, B. Liu, Q. Zhou, X. L. Hong, Voltage Island Generation in Cell Based Dual-Vdd Design, IEICE Trans. Fundamentals of Electronic, Communications and Computer Science, Vol. E90-A, No.1, PP.267-273, 2007.

[10] W. X. Shen, Y. C. Cai, X. L. Hong, Activity and Register placement Aware Gated Clock Tree Design, in Prof. International Symposium on Physical Design (ISPD 2008), Portland, Oregon, USA, 2008, PP.182-189.

[11] Shen Weixiang, Cai Yici, Hong Xianlong, An Effective Gated Clock Network Design Based on Activity and Register Aware Placement, IEEE Trans. on Very Large Scale Integration Systems (TVLSI), (to appear).

[12] H. Yao, S. Sinha, C. Chiang, X. Hong and Y. Cai, "Efficient Process-hotspot Detection Using Range Pattern Matching," Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2006), San Jose, USA, Nov. 2006, pp. 625-632. (Best Paper Nomination)

[13] H. Yao, S. Sinha, J. Xu, C. Chiang, Y. Cai and X. Hong, "Efficient range pattern matching algorithm for process-hotspot detection," IET Circuits, Devices & Systems, Vol.2, No. 1, pp. 2-15, 2008.

[14] Y. Shen, Q. Zhou, Y. C. Cai, X. L. Hong, ECP and CMP Aware Detailed Routing Algorithms for DFM, IEEE Trans. On Very Large Scale Integration Systems (TVLSI), Vol.18, No. 1, PP.153-157, 2010.

[15] X. Hong, Y. Cai, H. Yao and D. Li, "DFM-aware Routing for Yield Enhancement," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, Singapore, Dec. 2006, pp. 1093-1096. (Invited paper)

[16] Jia Yanming, Cai Yici, Hong Xianlong, Dummy Fill Aware Buffer Insertion After Layer Assignment Based On An Effective Estimation Model, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E91-A, No.12, 2008, pp.3783-3792.

教育部科技进步二等奖——超大规模集成电路物理级优化和验证问题基础研究(2006)。

DAC2009：最佳论文提名奖(2009)。

ICCAD2006：最佳论文提名奖(2006)。

GLVLSI2008：最佳论文奖(2008)。

清华大学：教学优秀奖(2000)。